Method of forming bus line designs for large-area OLED lighting

ABSTRACT

Systems, and methods for the design and fabrication of OLEDs, including large-area OLEDs with metal bus lines, are provided. For a given panel area dimension, target luminous emittance, OLED device structure and efficiency (as given by the JVL characteristics of an equivalent small area pixel), and electrical resistivity and thickness of the bus line material and electrode onto which the bus lines are disposed, a bus line pattern may be designed such that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL) may be optimized. One general design objective may be to maximize FF, maximize U and minimize PL. Another approach may be, for example, to define minimum criteria for U and a maximum criteria for PL, and then to optimize the bus line layout to maximize FF. OLED panels including bus lines with different resistances (R 1 ) along a length of the bus line are also described.

PARTIES TO A JOINT RESEARCH AGREEMENT

The claimed invention was made by, on behalf of, and/or in connectionwith one or more of the following parties to a joint universitycorporation research agreement: Regents of the University of Michigan,Princeton University, University of Southern California, and theUniversal Display Corporation. The agreement was in effect on and beforethe date the claimed invention was made, and the claimed invention wasmade as a result of activities undertaken within the scope of theagreement.

FIELD OF THE INVENTION

The present invention relates to systems, and processes for fabricatingOLED lighting panels, and particularly for designing and forming metalbus lines as may be used in large-area OLED lighting panels.

BACKGROUND

Opto-electronic devices that make use of organic materials are becomingincreasingly desirable for a number of reasons. Many of the materialsused to make such devices are relatively inexpensive, so organicopto-electronic devices have the potential for cost advantages overinorganic devices. In addition, the inherent properties of organicmaterials, such as their flexibility, may make them well suited forparticular applications such as fabrication on a flexible substrate.Examples of organic opto-electronic devices include organic lightemitting devices (OLEDs), organic phototransistors, organic photovoltaiccells, and organic photodetectors. For OLEDs, the organic materials mayhave performance advantages over conventional materials. For example,the wavelength at which an organic emissive layer emits light maygenerally be readily tuned with appropriate dopants.

OLEDs make use of thin organic films that emit light when voltage isapplied across the device. OLEDs are becoming an increasinglyinteresting technology for use in applications such as flat paneldisplays, illumination, and backlighting. Several OLED materials andconfigurations are described in U.S. Pat. Nos. 5,844,363, 6,303,238, and5,707,745, which are incorporated herein by reference in their entirety.

One application for phosphorescent emissive molecules is a full colordisplay. Industry standards for such a display call for pixels adaptedto emit particular colors, referred to as “saturated” colors. Inparticular, these standards call for saturated red, green, and bluepixels. Color may be measured using CIE coordinates, which are wellknown to the art.

One example of a green emissive molecule is tris(2-phenylpyridine)iridium, denoted Ir(ppy)₃, which has the following structure:

In this, and later figures herein, we depict the dative bond fromnitrogen to metal (here, Ir) as a straight line.

As used herein, the term “organic” includes polymeric materials as wellas small molecule organic materials that may be used to fabricateorganic opto-electronic devices. “Small molecule” refers to any organicmaterial that is not a polymer, and “small molecules” may actually bequite large. Small molecules may include repeat units in somecircumstances. For example, using a long chain alkyl group as asubstituent does not remove a molecule from the “small molecule” class.Small molecules may also be incorporated into polymers, for example as apendent group on a polymer backbone or as a part of the backbone. Smallmolecules may also serve as the core moiety of a dendrimer, whichconsists of a series of chemical shells built on the core moiety. Thecore moiety of a dendrimer may be a fluorescent or phosphorescent smallmolecule emitter. A dendrimer may be a “small molecule,” and it isbelieved that all dendrimers currently used in the field of OLEDs aresmall molecules.

As used herein, “top” means furthest away from the substrate, while“bottom” means closest to the substrate. Where a first layer isdescribed as “disposed over” a second layer, the first layer is disposedfurther away from substrate. There may be other layers between the firstand second layer, unless it is specified that the first layer is “incontact with” the second layer. For example, a cathode may be describedas “disposed over” an anode, even though there are various organiclayers in between.

As used herein, “solution processible” means capable of being dissolved,dispersed, or transported in and/or deposited from a liquid medium,either in solution or suspension form.

A ligand may be referred to as “photoactive” when it is believed thatthe ligand directly contributes to the photoactive properties of anemissive material. A ligand may be referred to as “ancillary” when it isbelieved that the ligand does not contribute to the photoactiveproperties of an emissive material, although an ancillary ligand mayalter the properties of a photoactive ligand.

As used herein, and as would be generally understood by one skilled inthe art, a first “Highest Occupied Molecular Orbital” (HOMO) or “LowestUnoccupied Molecular Orbital” (LUMO) energy level is “greater than” or“higher than” a second HOMO or LUMO energy level if the first energylevel is closer to the vacuum energy level. Since ionization potentials(IP) are measured as a negative energy relative to a vacuum level, ahigher HOMO energy level corresponds to an IP having a smaller absolutevalue (an IP that is less negative). Similarly, a higher LUMO energylevel corresponds to an electron affinity (EA) having a smaller absolutevalue (an EA that is less negative). On a conventional energy leveldiagram, with the vacuum level at the top, the LUMO energy level of amaterial is higher than the HOMO energy level of the same material. A“higher” HOMO or LUMO energy level appears closer to the top of such adiagram than a “lower” HOMO or LUMO energy level.

As used herein, and as would be generally understood by one skilled inthe art, a first work function is “greater than” or “higher than” asecond work function if the first work function has a higher absolutevalue. Because work functions are generally measured as negative numbersrelative to vacuum level, this means that a “higher” work function ismore negative. On a conventional energy level diagram, with the vacuumlevel at the top, a “higher” work function is illustrated as furtheraway from the vacuum level in the downward direction. Thus, thedefinitions of HOMO and LUMO energy levels follow a different conventionthan work functions.

As used herein, a small area pixel is “equivalent” to a large area panelif (1) the organic stack of the small area pixel consists essentially ofthe organic layers of the organic stack of the large area panel; (2) theorganic stack of the small area pixel is structurally equivalent to theorganic stack of the large area panel; and/or (3) the organic stack ofthe small area pixel is functionally equivalent to the organic stack ofthe large area panel.

As used herein, the organic stack of a small area pixel “consistsessentially of” the organic layers of the organic stack of a large areapanel if the organic stack of the small area pixel is expected to have asimilar JVL characteristic (where “J” is current density and “V” isvoltage and “L” is luminance) as the organic stack of the large areapanel. That is, the organic stack of the small area pixel will performin the same way as the organic stack in the large area pixel. By usingthis terminology, it is intended to encompass a situation where devicesare not exactly identical, but the differences comprise, for instance,only a slight change to the thickness of a layer; a slight modificationto a concentration of one of the layers; a material substitution with amaterial known to behave in the same way, and/or other smallmodifications such that a person of ordinary skill in the art wouldunderstand that the devices would function the same way for purposes oflifetime testing. These situations, and other differences that do notmaterially affect the characteristics and function of the device, areintended to be covered by this language.

As used herein, a first organic stack is “structurally equivalent” to asecond organic stack if the first organic stack comprises materials thatare the same as the second organic stack, and the thickness andconcentrations levels of these materials (while not necessarilyprecisely identical) are within experimental error. For instance, thethickness and concentrations of each of the layers of the first organicstack may be within 5% of the corresponding layers in the second organicstack.

As used herein, a first organic stack is “functionally equivalent” to asecond organic stack if the first organic stack comprises the samelayers as the second organic stack, with only variations that do notsignificantly affect the JVL characteristics of the organic stack. Thevariations may be in any form, by way of example, differences inthickness, concentrations, and/or material. If one of skill in the artbelieves that lifetime data from one device can reasonably be used topredict the lifetime of another device that is expected to have asimilar lifetime, the devices are “functionally equivalent.”

More details on OLEDs, and the definitions described above, can be foundin U.S. Pat. No. 7,279,704, which is incorporated herein by reference inits entirety.

In large area OLED light panels, potential drops due to significantelectrode resistances can cause luminance non-uniformity and reducedevice efficacy. One method used to reduce potential drops is tointroduce highly conductive bus lines. Bus lines are typically designedto deliver current from the electrode contacts and to distribute currentevenly across the OLED light panel. Current distribution is thendependent on bus line resistance, electrode resistance, active area andthe particular JVL characteristics of the OLED stack. Bus lineresistance is determined by the resistivity of the bus line material andthe geometry of the bus line, including thickness, length and width. Inprinciple, the resistance of the bus lines could be reduced by using amaterial with lower resistivity (such as gold, silver, aluminum orcopper) or increasing the height of the bus line. However, in practice,there is a finite height at which it is practical to deposit a busline—any higher than, and it becomes difficult to dispose uniform thinfilms over the bus lines. Further reduction in the resistance is thentypically achieved by increasing the width of the bus lines.

One drawback of using bus lines in OLEDs is that there is usually nolight emission from the organic materials disposed over the bus lines.This means that the greater the area of the bus lines, the smaller thearea that is available for light emission. When characterizing largearea OLED light panels, a critical parameter is luminous emittance inunits of lm/m², which expresses total light output delivered per unitarea from the panel. For an approximately Lambertian emitter, luminousemittance (lm/m²)=π×luminance (cd/m²)×Fill Factor, where Fill. Factor isthe percentage of the OLED light panel area for which recombination andlight emission is enabled. The lower the total area of the bus lines,the greater the Fill Factor and the lower the luminance that is thenneeded to deliver the same luminous emittance. This requirement forlower luminance, leads to improved lifetime and efficacy for OLED lightpanels with higher Fill Factor.

SUMMARY OF THE INVENTION

In view of the foregoing, it has been recognized that it is importantnot to pattern bus lines with an excessively large area. According toaspects of the invention, systems, and methods for the design andfabrication of OLEDs, including large-area OLEDs with metal bus lines,are provided. In embodiments various bus line design rules for largearea OLED light panels may include mathematical models developed tooptimize bus line design and/or layout on large area OLED light panels.In embodiments, for a given panel area dimension, target luminousemittance, OLED device structure and efficiency (as given by the JVLcharacteristics of an equivalent small area pixel), and electricalresistivity and thickness of the bus line material and electrode ontowhich the bus lines are disposed, a bus line pattern may be designedsuch that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL)may be optimized. One general design objective may be to maximize FF,maximize U and minimize PL. Another approach may be, for example, todefine minimum criteria for U and a maximum criteria for PL, and then tooptimize the bus line layout to maximize FF. Note that for theequivalent small area pixel it is assumed that there is negligiblepotential drop in delivering charge to the OLED device. The equivalentpixel is required to have substantially the same organic layer devicestructure as in the OLED light panel.

As used herein, the inventors define luminous uniformityU=L_(min)/L_(max), where luminance is measured at normal incidencedirectly over an active OLED area, and FF=(Panel Area−Bus LineArea)/Panel Area, where Panel Area is the area defined by the outline ofthe total plurality of Active Areas with surrounding Bus Line Areas. BusLine Area includes surface area of bus lines and insulating coverage(optional). Panel Area is typically less than the Substrate Area, whichincludes encapsulation area and contact pads etc. Exemplary methods mayinclude, for example, optimization of large area OLED light panel FF, Uand PL using bus lines of fixed width, and optimization of large areaOLED light panel FF, U and PL using bus lines of variable width.

According to first aspects of the invention, a method of manufacturing alight emitting panel, with a plurality of active areas, a plurality ofbus lines and at least one pair of electrode contacts with the samepolarity, may include determining equipotential lines on at least oneelectrode in the absence of bus lines. Embodiments may includedetermining an arrangement for a plurality of bus lines between the atleast one pair of electrode contacts, the plurality of bus linesarranged to run substantially perpendicular to the determinedequipotential lines.

Embodiments may include forming the plurality of bus lines in electricalcontact with the electrode according to the determined arrangement.

In embodiments, the at least one pair of electrode contacts may includea pair of anode contacts, the electrode is anode, and the plurality ofbus lines may be arranged between the pair of anode contacts.

In embodiments, the at least one pair of electrode contacts may includea pair of cathode contacts, the electrode is cathode, and the pluralityof bus lines may be arranged between the pair of cathode contacts, suchas in a top-emission OLED.

In embodiments, the equipotential lines may be determined for a firstelectrode and a second electrode; the at least one pair of electrodecontacts may include a first set of electrode contacts for the firstelectrode and a second set of electrode contacts for the secondelectrode; a first set of the plurality of bus lines may be arrangedbetween the first set of electrode contacts and a second set of theplurality of bus lines may be arranged between the second set ofelectrode contacts; and the first set of bus lines may be formed inelectrical contact with the first electrode and the second set of buslines may be formed in electrical contact with the second electrode.Such embodiments may include, for example, a substantially transparentOLED device.

In embodiments, the panel area may be substantially rectangular, with afirst set of electrode contacts of the same electrical polarity onopposite sides of the electrode. The plurality of bus lines may bearranged in electrical contact with the electrode to closely runsubstantially perpendicular to the first set of electrode contacts.

In embodiments, the panel area may be substantially rectangular andinclude a first electrode and a second electrode, the second electrodeseparate, and opposite electrical polarity, from the first electrode.The equipotential lines may be determined for the first electrode andthe second electrode. In embodiments, the at least one pair of electrodecontacts may include a first set of electrode contacts, for the firstelectrode, and a second set of electrode contacts, for the secondelectrode. A first set of bus lines may be arranged between the firstset of electrode contacts and a second set bus lines may be arrangedbetween the second set of electrode contacts. The first set of bus linesmay be formed in electrical contact with the first electrode andsubstantially perpendicular to the first set of electrode contacts, andthe second set of bus lines may be formed in electrical contact with thesecond electrode and substantially perpendicular to the second set ofelectrode contacts. In embodiments, the first set of electrode contactsmay be anode contacts. In embodiments, the first set of electrodecontacts may be cathode contacts.

In embodiments, exemplary panel areas may be substantially rectangularand include electrode contacts of the same polarity on each side of thepanel area. In such embodiments, the plurality of bus lines may bearranged such that a first set of the bus lines closely runsubstantially perpendicular to one pair of opposing sides of the panelarea, and a second set of the bus lines closely run substantiallyperpendicular to the other pair of opposing sides of the panel area. Thefirst set of the bus lines and the second set of the bus lines may be inelectrical contact with the same electrode.

In embodiments, a first pair of opposing sides of the panel area mayhave a relatively long length compared to a second pair of opposingsides of the panel area. Electrode contacts of the same polarity may beincluded on at least the first pair of opposing sides of the panel area,and the plurality of bus lines may be arranged to closely run onlysubstantially perpendicular to the first pair of opposing sides of thepanel area.

In embodiments, the panel area may include a plurality of substantiallyrectangular active areas. In embodiments, first pairs of opposing sidesof the active areas may have a relatively long length compared to secondpairs of opposing sides of the active areas, and the active areas may bearranged such that the first pair of opposing sides of the active areasclosely run substantially parallel to the plurality of bus lines.

In embodiments, the panel area may include a circular shape and theequipotential lines may be concentric. The bus lines may be arranged,for example, to run along radii extending from an edge of the circularshape to a center of the circular shape.

Embodiments may include calculating a minimum bus line width for theplurality of bus lines based on a given target working condition; andthe plurality of bus lines may be formed according to the calculatedminimum bus line width. The working condition could be a target luminousemittance and one or the combination of two of a minimum Uniformity, aminimum Fill Factor or a maximum Power Loss.

In embodiments, the calculating of the minimum bus line width mayinclude providing horizontal dimensions of the panel area; providingresistivity values and thickness of the bus line material and theelectrode onto which the bus line is disposed, providing JVLcharacteristics of an equivalent small area pixel, and optimizing valuesfor at least one of a maximum Fill Factor, a maximum luminanceUniformity and a minimum Power Loss for the working condition.

In embodiments, a footprint of the outer dimensions of the at least onepair of electrode contacts may be equal to or larger than a perimeterfootprint of the panel area.

According to further aspects of the invention, a method of manufacturinga light emitting panel with a plurality of active areas and a pluralityof bus lines, may include providing horizontal dimensions of the panelarea; providing device current density-voltage-luminance (JVL) data ofan equivalent small area pixel; providing resistivity values andthickness of the bus line material and the electrode onto which the busline is disposed; providing a target working condition for the lightemitting panel; calculating at least one width of metal bus lines basedon the horizontal dimensions of the panel area, device JVL data,resistivity and thickness of bus line material and the electrode ontowhich the bus line is disposed, and the target working condition; and/orforming the plurality of bus lines according to the at least onecalculated value.

In embodiments, the panel area may comprise one or more active areas.The calculating of the at least one width of metal bus lines may includeproviding a length of at least one active area (S) and a height of thisone active area (H). In embodiments, the calculating of the at least onewidth of metal bus lines may include calculating at least one of a widthof metal bus lines along an x direction (W_(x)) and width of metal buslines along a y direction (W_(y)), based on S, H, horizontal dimensionsof the panel area, device JVL data, resistivity and thickness of busline material and the electrode onto which the bus line is disposed, andthe target working condition.

In embodiments, the panel area may be rectangular with length X andwidth Y, and FF may be solved according to the equation:

${FF} = \frac{{X \cdot Y} - {\sum\limits_{m = 1}^{n}A_{m}}}{X \cdot Y}$

wherein, A_(m) is the non-active surface area within the panel areacaused by the presence of each bus line segment (this may include thebus line and the insulating material that covers the bus line).

In embodiments with a bus line running along a y direction, each segmentof the bus line may have a resistivity ρ(y), thickness t(y), and widthW_(x)(y), and an angle θ(y) with respect to y, and the calculating ofthe at least one of W_(x) and W_(y) may include solving for a potentialdrop (ΔV) along the bus line of length L according to the equation:

${\Delta\; V} = {\overset{L}{\int\limits_{0}}{{\rho(y)}\frac{{\overset{->}{I}(y)}}{\cos^{2}{\theta(y)}{{{\overset{->}{W}}_{x}(y)}}{t(y)}}{{\mathbb{d}y}}}}$

In embodiments, the calculating at least one width of metal bus linesmay include solving for a Fill Factor (FF)>70% and a LuminanceUniformity (U)>80%. In embodiments, the light emitting panel may have apanel area, for example, >50 cm², and the calculating at least one widthof metal bus lines may include solving for a FF>80% and a U>90%, orsolving for a FF>90% and a U>90%.

In embodiments, the bus lines may be formed to run substantiallyperpendicular to the equipotential lines. Additionally, the panel areamay operate at an average luminous emittance greater than 8,000 lm/m²inclusive of light extraction enhancement. This average luminousemittance may include the active area and the non-emissive bus linesbetween the active areas.

According to further aspects of the invention, a light emitting devicemay include a panel with a first electrode layer and an organic layerstack over the first electrode layer. A second electrode layer may beover the organic layer stack. At least one pair of first electrodecontacts with the same electrical polarity may be provided in electricalcontact with at least one of the first electrode layer and the secondelectrode layer. A plurality of bus lines may be included in electricalcontact with the first electrode contacts and at least one of the firstelectrode layer and the second electrode layer. The bus lines may bedisposed, for example, over the first electrode layer, under the firstelectrode layer, over the second electrode layer and/or under the secondelectrode layer. In embodiments, the panel area may have an area >50cm², a Fill Factor (FF)>70% and a Luminance Uniformity (U)>80%.

In embodiments, the electrode contacts connected to the bus lines may beanode contacts, and the device may be a bottom-emitting OLED. Inembodiments, the electrode contacts connected to the bus lines may becathode contacts, and the device may be a top-emitting OLED. Inembodiments, the electrode contacts may include a pair of anode contactsand a pair of cathode contacts, and a first set of bus lines may bearranged between the pair of anode contacts and a second set of the buslines may be arranged between the pair of cathode contacts, and thedevice may be a transparent OLED.

In embodiments, the FF may be >80% and the U may be >90%, or the FF maybe >90% and the U may be >90%.

In embodiments, the bus lines may be formed to run substantiallyperpendicular to equipotential lines.

In embodiments, the panel area may be configured to operate at anaverage luminous emittance greater than 8,000 μm/m² inclusive of lightextraction enhancement.

In embodiments, a plurality of active areas may be arranged in the panelarea, and at least one fuse may be connected to bus lines for each ofthe plurality of active areas.

In embodiments, the light emitting panel may include a Color RenderingIndex (CRI) R_(a)>80 and a Duv<0.010.

In embodiments, electrode contacts may be disposed on all sides of thepanel area. In embodiments, a footprint of the electrode contact may beequal to or larger than a perimeter footprint of the panel area.

According to further aspects of the invention, a light emitting devicemay include a first electrode layer, one or more first electrodecontacts, an organic layer stack, a second electrode layer, one or moresecond electrode contacts, and a plurality of bus lines. In embodiments,the first electrode layer may have a same electrical polarity as thefirst electrode contacts, and/or the second electrode layer may have asame electrical polarity as the second electrode contacts. The pluralityof bus lines may be in electrical contact with, for example, the firstelectrode layer and the first electrode contacts, and/or the secondelectrode layer and the second electrode contacts. In embodiments, atleast one of the plurality of bus lines may include differentresistances (R₁) along a length of the at least one bus line.

In embodiments, a cross sectional area of the at least one bus line maydecrease along the length. In embodiments, at least one of a width and aheight of the at least one bus line may monotonically decrease along thelength.

In embodiments, the at least one bus line may include differentmaterials with different conductivities.

In embodiments, R₁ may be lowest at an electrode contact end of the atleast one bus line.

In embodiments, at least one of the electrode layers may include a firstcontact of the electrode and a second contact of the electrode oppositethe first contact of the electrode. A first bus line may extend from thefirst contact of the electrode toward the second contact of theelectrode and a second bus line may extend from the second contact ofthe electrode toward the first contact of the electrode. In embodiments,a width of the first bus line may decrease toward the second contact ofthe electrode, and a width of the second bus line may decrease towardthe first contact of the electrode.

In embodiments, the bus lines may be tapered with a maximum width at anelectrode contact end, and a minimum width at a distance greatest fromthe contact.

In embodiments, a luminance gradient dL/dx across the panel area may beapproximately constant, e.g. (dL/dx)_(min)/(dL/dx)_(max) greater than0.5.

In embodiments, the voltage of the panel may be equal to or less than0.2V greater than an equivalent small area pixel at the same currentdensity.

Additional features, advantages, and embodiments of the invention may beset forth or apparent from consideration of the following detaileddescription, drawings, and claims. Moreover, it is to be understood thatboth the foregoing summary of the invention and the following detaileddescription are exemplary and intended to provide further explanationwithout limiting the scope of the invention claimed. The detaileddescription and the specific examples, however, indicate only preferredembodiments of the invention. Various changes and modifications withinthe spirit and scope of the invention will become apparent to thoseskilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention, are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the detailed description serve to explain the principlesof the invention. No attempt is made to show structural details of theinvention in more detail than may be necessary for a fundamentalunderstanding of the invention and various ways in which it may bepracticed. In the drawings:

FIG. 1 shows an organic light emitting device.

FIG. 2 shows an inverted organic light emitting device that does nothave a separate electron transport layer.

FIG. 3 shows an exemplary related-art device including bus lines.

FIG. 4 shows a schematic diagram of an OLED configuration with anode andcathode contacts.

FIG. 5 shows a schematic diagram of an OLED configuration according toaspects of the invention.

FIG. 6 shows a 4 section pattern of a 15 cm×15 cm OLED light panelaccording to aspects of the invention.

FIG. 7 shows a microscope picture of bus lines within each section.

FIG. 8 shows four units, where each unit is surrounded by metal buslines (shadow regions).

FIGS. 9A-9B show exemplary OLED circuits according to aspects of theinvention.

FIG. 10 shows various aspects of calculations for bus line resistancesaccording to aspects of the invention.

FIG. 11 shows Fill Factor plotted against W_(x) and W_(y) for a squareOLED light panel with H=S=1 mm (squares) and H=S=10 mm (circles).

FIGS. 12A-12B show impact of W_(x) and W_(y) on panel non-uniformity andpower loss for an active area unit size of 1 mm×1 mm and 10 mm×10 mm(with contacts only along y axis).

FIG. 13 shows a square OLED panel with anode contacts on four edgesaccording to aspects of the invention.

FIG. 14 depicts an OLED lighting panel with anode contacts on four edgesand a grid-pattern bus line.

FIG. 15 depicts a circle-shape panel with anode contacts around thecircumference.

FIG. 16 shows a stripe design, with bus lines on two longer sides of theactive area.

FIG. 17 shows an OLED stack.

FIG. 18 is an image of an OLED lighting panel with stripes of pixels;

FIG. 19 is a normalized luminance and luminance gradient along bus line.

FIG. 20 depicts aspects of a non-uniform patterned bus line layout.

FIG. 21 is an illustration of bus lines A, B and C from Table 4.

FIG. 22 is a chart showing normalized luminance and luminance gradient.

FIG. 23 depicts an example of non-uniform patterned bus line in a spiralshape, with luminance measured at the numbered spots.

DETAILED DESCRIPTION

It is understood that the invention is not limited to the particularmethodology, protocols, and reagents, etc., described herein, as thesemay vary as the skilled artisan will recognize. It is also to beunderstood that the terminology used herein is used for the purpose ofdescribing particular embodiments only, and is not intended to limit thescope of the invention. It also is be noted that as used herein and inthe appended claims, the singular forms “a,” “an,” and “the” include theplural reference unless the context clearly dictates otherwise. Thus,for example, a reference to “a bus line” is a reference to one or morebus lines and equivalents thereof known to those skilled in the art.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meanings as commonly understood by one of ordinary skillin the art to which the invention pertains. The embodiments of theinvention and the various features and advantageous details thereof areexplained more fully with reference to the non-limiting embodiments andexamples that are described and/or illustrated in the accompanyingdrawings and detailed in the following description. It should be notedthat the features illustrated in the drawings are not necessarily drawnto scale, and features of one embodiment may be employed with otherembodiments as the skilled artisan would recognize, even if notexplicitly stated herein. Descriptions of well-known components andprocessing techniques may be omitted so as to not unnecessarily obscurethe embodiments of the invention. The examples used herein are intendedmerely to facilitate an understanding of ways in which the invention maybe practiced and to further enable those of skill in the art to practicethe embodiments of the invention. Accordingly, the examples andembodiments herein should not be construed as limiting the scope of theinvention, which is defined solely by the appended claims and applicablelaw. Moreover, it is noted that like reference numerals referencesimilar parts throughout the several views of the drawings.

The following preferred embodiments may be described in the context ofexemplary OLED devices for ease of description and understanding.However, the invention is not limited to the specifically describeddevices and methods, and may be adapted to various circuit assemblieswithout departing from the overall scope of the invention. For example,devices and related methods including concepts described herein may beused for the assembly of microchips, optoelectronic devices, such assolar cells and photodetectors, and other apparatus with multi-layercircuitry.

Generally, an OLED comprises at least one organic layer disposed betweenand electrically connected to an anode and a cathode. When a current isapplied, the anode injects holes and the cathode injects electrons intothe organic layer(s). The injected holes and electrons each migratetoward the oppositely charged electrode. When an electron and holelocalize on the same molecule, an “exciton,” which is a localizedelectron-hole pair having an excited energy state, is formed. Light isemitted when the exciton relaxes via a photoemissive mechanism. In somecases, the exciton may be localized on an excimer or an exciplex.Non-radiative mechanisms, such as thermal relaxation, may also occur,but are generally considered undesirable.

The initial OLEDs used emissive molecules that emitted light from theirsinglet states (“fluorescence”) as disclosed, for example, in U.S. Pat.No. 4,769,292, which is incorporated by reference in its entirety.Fluorescent emission generally occurs in a time frame of less than 10nanoseconds.

More recently, OLEDs having emissive materials that emit light fromtriplet states (“phosphorescence”) have been demonstrated. Baldo et al.,“Highly Efficient Phosphorescent Emission from OrganicElectroluminescent Devices,” Nature, vol. 395, 151-154, 1998;(“Baldo-I”) and Baldo et al., “Very high-efficiency green organiclight-emitting devices based on electrophosphorescence,” Appl. Phys.Lett., vol. 75, No. 3, 4-6 (1999) (“Baldo-II”), which are incorporatedby reference in their entireties. Phosphorescence is described in moredetail in U.S. Pat. No. 7,279,704 at cols. 5-6, which are incorporatedby reference.

FIG. 1 shows an organic light emitting device 100. The figures are notnecessarily drawn to scale. Device 100 may include a substrate 110, ananode 115, a hole injection layer 120, a hole transport layer 125, anelectron blocking layer 130, an emissive layer 135, a hole blockinglayer 140, an electron transport layer 145, an electron injection layer150, a protective layer 155, and a cathode 160. Cathode 160 is acompound cathode having a first conductive layer 162 and a secondconductive layer 164. Device 100 may be fabricated by depositing thelayers described, in order. The properties and functions of thesevarious layers, as well as example materials, are described in moredetail in U.S. Pat. No. 7,279,704 at cols. 6-10, which are incorporatedby reference.

More examples for each of these layers are available. For example, aflexible and transparent substrate-anode combination is disclosed inU.S. Pat. No. 5,844,363, which is incorporated by reference in itsentirety. An example of a p-doped hole transport layer is m-MTDATA dopedwith F.sub.4-TCNQ at a molar ratio of 50:1, as disclosed in U.S. PatentApplication Publication No. 2003/0230980, which is incorporated byreference in its entirety. Examples of emissive and host materials aredisclosed in U.S. Pat. No. 6,303,238 to Thompson et al., which isincorporated by reference in its entirety. An example of an n-dopedelectron transport layer is BPhen doped with Li at a molar ratio of 1:1,as disclosed in U.S. Patent Application Publication No. 2003/0230980,which is incorporated by reference in its entirety. U.S. Pat. Nos.5,703,436 and 5,707,745, which are incorporated by reference in theirentireties, disclose examples of cathodes including compound cathodeshaving a thin layer of metal such as Mg:Ag with an overlyingtransparent, electrically-conductive, sputter-deposited ITO layer. Thetheory and use of blocking layers is described in more detail in U.S.Pat. No. 6,097,147 and U.S. Patent Application Publication No.2003/0230980, which are incorporated by reference in their entireties.Examples of injection layers are provided in U.S. Patent ApplicationPublication No. 2004/0174116, which is incorporated by reference in itsentirety. A description of protective layers may be found in U.S. PatentApplication Publication No. 2004/0174116, which is incorporated byreference in its entirety.

FIG. 2 shows an inverted OLED 200. The device includes a substrate 210,a cathode 215, an emissive layer 220, a hole transport layer 225, and ananode 230. Device 200 may be fabricated by depositing the layersdescribed, in order. Because the most common OLED configuration has acathode disposed over the anode, and device 200 has cathode 215 disposedunder anode 230, device 200 may be referred to as an “inverted” OLED.Materials similar to those described with respect to device 100 may beused in the corresponding layers of device 200. FIG. 2 provides oneexample of how some layers may be omitted from the structure of device100.

The simple layered structure illustrated in FIGS. 1 and 2 is provided byway of non-limiting example, and it is understood that embodiments ofthe invention may be used in connection with a wide variety of otherstructures. The specific materials and structures described areexemplary in nature, and other materials and structures may be used.Functional OLEDs may be achieved by combining the various layersdescribed in different ways, or layers may be omitted entirely, based ondesign, performance, and cost factors. Other layers not specificallydescribed may also be included. Materials other than those specificallydescribed may be used. Although many of the examples provided hereindescribe various layers as comprising a single material, it isunderstood that combinations of materials, such as a mixture of host anddopant, or more generally a mixture, may be used. Also, the layers mayhave various sublayers. The names given to the various layers herein arenot intended to be strictly limiting. For example, in device 200, holetransport layer 225 transports holes and injects holes into emissivelayer 220, and may be described as a hole transport layer or a holeinjection layer. In one embodiment, an OLED may be described as havingan “organic layer” disposed between a cathode and an anode. This organiclayer may comprise a single layer, or may further comprise multiplelayers of different organic materials as described, for example, withrespect to FIGS. 1 and 2.

Structures and materials not specifically described may also be used,such as OLEDs comprised of polymeric materials (PLEDs) such as disclosedin U.S. Pat. No. 5,247,190 to Friend et al., which is incorporated byreference in its entirety. By way of further example, OLEDs having asingle organic layer may be used. OLEDs may be stacked, for example asdescribed in U.S. Pat. No. 5,707,745 to Forrest et al, which isincorporated by reference in its entirety. The OLED structure maydeviate from the simple layered structure illustrated in FIGS. 1 and 2.For example, the substrate may include an angled reflective surface toimprove out-coupling, such as a mesa structure as described in U.S. Pat.No. 6,091,195 to Forrest et al., and/or a pit structure as described inU.S. Pat. No. 5,834,893 to Bulovic et al., which are incorporated byreference in their entireties.

Unless otherwise specified, any of the layers of the various embodimentsmay be deposited by any suitable method. For the organic layers,preferred methods include thermal evaporation, ink-jet, such asdescribed in U.S. Pat. Nos. 6,013,982 and 6,087,196, which areincorporated by reference in their entireties, organic vapor phasedeposition (OVPD), such as described in U.S. Pat. No. 6,337,102 toForrest et al., which is incorporated by reference in its entirety, anddeposition by organic vapor jet printing (OVJP), such as described inU.S. patent application Ser. No. 10/233,470, which is incorporated byreference in its entirety. Other suitable deposition methods includespin coating and other solution based processes. Solution basedprocesses are preferably carried out in nitrogen or an inert atmosphere.For the other layers, preferred methods include thermal evaporation.Preferred patterning methods include deposition through a mask, coldwelding such as described in U.S. Pat. Nos. 6,294,398 and 6,468,819,which are incorporated by reference in their entireties, and patterningassociated with some of the deposition methods such as ink-jet and OVJD.Other methods may also be used. The materials to be deposited may bemodified to make them compatible with a particular deposition method.For example, substituents such as alkyl and aryl groups, branched orunbranched, and preferably containing at least 3 carbons, may be used insmall molecules to enhance their ability to undergo solution processing.Substituents having 20 carbons or more may be used, and 3-20 carbons isa preferred range. Materials with asymmetric structures may have bettersolution processibility than those having symmetric structures, becauseasymmetric materials may have a lower tendency to recrystallize.Dendrimer substituents may be used to enhance the ability of smallmolecules to undergo solution processing.

Devices fabricated in accordance with embodiments of the invention maybe incorporated into a wide variety of consumer products, including flatpanel displays, computer monitors, televisions, billboards, lights forinterior or exterior illumination and/or signaling, heads up displays,fully transparent displays, flexible displays, laser printers,telephones, cell phones, personal digital assistants (PDAs), laptopcomputers, digital cameras, camcorders, viewfinders, micro-displays,vehicles, a large area wall, theater or stadium screen, or a sign.Various control mechanisms may be used to control devices fabricated inaccordance with the present invention, including passive matrix andactive matrix. Many of the devices are intended for use in a temperaturerange comfortable to humans, such as 18 degrees C. to 30 degrees C., andmore preferably at room temperature (20-25 degrees C.).

The materials and structures described herein may have applications indevices other than OLEDs. For example, other optoelectronic devices suchas organic solar cells and organic photodetectors may employ thematerials and structures. More generally, organic devices, such asorganic transistors, may employ the materials and structures.

The terms halo, halogen, alkyl, cycloalkyl, alkenyl, alkynyl, arylkyl,heterocyclic group, aryl, aromatic group, and heteroaryl are known tothe art, and are defined in U.S. Pat. No. 7,279,704 at cols. 31-32,which are incorporated herein by reference.

As mentioned previously, bus lines may be used to reduce potential dropsin large area OLED light panels, thereby reducing luminancenon-uniformity and enhancing device efficacy. According to aspects ofthe invention, lighting panels including bus lines, and having bothrelatively high degree of Luminance Uniformity (U) and Fill Factor (FF),may be provided. In general, U and FF typically go against one another.However, through various techniques described herein, the inventors havemodeled and produced devices achieving relatively high measures of U andFF together, particularly as compared to other known devices andtechniques. For example, as described further herein, exemplary OLEDdevices designed in accordance with aspects of the present subjectmatter have been shown to include U of approximately 89% with FF ofapproximately 93%, which compares exceptionally well with other knowndevices.

Related aspects of the invention may also include specifically optimizedbus line design techniques. Among other objects, the inventors haveshown that overall potential drop may favorably be minimized, based onits relationship to U, and, since the current varies depending on thedistance to the contact point, the resistance of the bus line may bevaried accordingly to achieve an improved overall result, e.g. a busline that is more conductive near the contact and less conductivefarther away. This has been shown to be beneficial in, for example,minimizing bus line foot print (maximizing FF) for a desired uniformity,or maximizing uniformity for a fixed FF requirement. Various embodimentsproviding further details of the foregoing concepts are discussedfurther below, and may generally be referred to in terms of, forexample, optimization of OLED light panel FF, U and PL using bus linesof fixed width, and optimization of large area OLED light panel FF, Uand PL using bus lines of variable width.

For ease of description, exemplary embodiments based on anode bus linesmay be discussed. Such configurations may find applicability, forexample, with bottom-emission or transparent OLEDs. However, it shouldbe appreciated that many of the same principles could be applied as wellto cathode bus lines, such as may be used in top-emission or transparentOLEDs.

Luminous uniformity may be understood as U=L_(min)/L_(max), whereL_(max) is the maximum luminance on the light panel and L_(min) is theminimum luminance on the light panel. Luminance may be understood asmeasured at normal incidence to the device directly over an OLED activearea. Non-Uniformity=1−U. Fill Factor may also be understood generallyas FF=(Panel Area−Bus Line Area)/Panel Area, where Panel Area is thearea defined by the outline of the total plurality of Active Areas withsurrounding Bus Line Areas. Bus Line area includes surface area of buslines and insulating coverage (optional). Panel Area is typically lessthan the Substrate Area, which includes encapsulation area and contactpads etc.

(A) Optimization of Large Area OLED Light Panel FF, U and PL Using BusLines of Fixed Width.

The inventors have found that, for a given panel dimension, targetluminous emittance, OLED device structure and efficiency (as given bythe JVL characteristics of an equivalent small area pixel), electricalresistivity and thickness of the bus line material and the electrodeonto which the bus lines are disposed, a bus line pattern may bedesigned such that Fill Factor (FF), Luminance Uniformity (U) and PowerLoss (PL) may be optimized. One general design objective may be tomaximize FF, maximize U and minimize PL. Another approach may be, forexample, to define minimum criteria for U and a maximum criteria for PL,and then to optimize the bus line layout to maximize FF. A given panelarea dimension and target luminous emittance may be advantageously usedto calculate the current flow in the panel. For example, for lowertarget luminous emittance, a lower current would be required, so buslines with higher resistance that occupy less of the Panel Area may beused.

It has also been noted that luminance non-uniformity may arise becauseof potential drops on the bus lines and because of potential dropswithin individual electrode areas. Thus, the dimensions and theorientation of the individual electrode areas should also be decidedupon certain criteria as well. For example the total panel areanon-uniformity can be expressed as the product of non-uniformity arisingfrom potential drops along the bus lines and non-uniformity arising frompotential drops across the electrode areas.

As a starting point, it is instructive to study an example of therelated art. FIG. 3 shows a schematic diagram of a related artcommercially available OLED light panel, “REF 1.” The total panel areais 49 cm², and the active area is approximately 48 cm². FF extractedfrom the diagram is about 98%. Nine points were marked on the panel, andluminance was measured at normal incidence to each point at V=4.2 V,I=0.607 A. Luminance values for each of the nine points are listed belowin Table 1.

TABLE 1 1 2 3 4 5 6 7 8 9 Lumi- 2990 2750 2750 2870 2340 2650 2700 26102900 nance (cd/m²)

The particular driving conditions were chosen such that average luminousfrom the panel area as measured inside a 20″ integrating sphere wasapproximately 9,000 μm/m² inclusive of approximately 1.5× lightextraction enhancement The luminance values in Table 1 suggest slightlylower luminous emittance owing to the angular dependence of theemission. The uniformity U=L_(min)/L_(max) calculated from the data is78%. Luminance is lowest at the center of the light panel, and highestby the anode contacts.

As shown in FIG. 3, a double-contact configuration is used in thispanel, where a pair of cathode contacts 310 are located at the top andbottom, and a pair of anode contacts 320 are on the right and left sidesof the panel area. A double-contact configuration where the contactsinclude at least one pair of electrode contacts of the same polarity atthe opposing sides of the panel area may, for example, enable betteruniformity than for an equivalent panel with a single-contactconfiguration. This is because the average current path length from thecontact is reduced in the double-contact configuration. This can lead toless IR loss in the device.

Nevertheless, the inventors have found that the contact design for thepanel shown in FIG. 3 is not ideal. This can be appreciated fromcomparing FIGS. 4 and 5.

As illustrated in “Mode A” shown in FIG. 4, current will be deliveredfrom the anode contact to the center through path 1. For current to beconducted towards the top and bottom of the panel area, longer paths 2and 3 are required. The longer paths cause more IR loss and thus greaterluminance non-uniformity.

On the contrary, “Mode B” shown in FIG. 5, includes additional anodecontacts added along the edges of the device. In this configuration,current can be delivered through shorter paths 4 and 5 to the top andbottom sides of the panel area, and therefore better uniformity can beachieved. FIGS. 4 and 5 show one way in which the present subject mattermay include the specific placement of, for example, the anode contacts,as well as optimizing the bus line design, may be used to minimize arequired bus line length.

Additional luminance non-uniformity may also arise in certain knownsystems due to the active area extending beyond the lateral extent ofthe contact pads to which the bus lines are connected. This means thatto illuminate the top and bottom edges of the light panel, current musttravel not only perpendicular to the contacts, but also in a paralleldirection to the contacts, which adds to the resistive loss andincreases the demand on the bus lines.

As can be appreciated from the foregoing discussion, in order to achievean optimized luminance uniformity, a minimum average current path lengthfrom electrode contacts to the active area may be designed into thepanel. This means the electrode contacts should be equal to or largerthan a perimeter footprint of the panel area. Also, double-contact, ormulti-contact configuration may be desired in large-area panel design,for example, to reduce the lengths of the required bus lines.

In embodiments, equipotential lines may also be used to help determinean optimal arrangement for the bus lines. For example, equipotentiallines on an electrode in the absence of bus lines, may be determined inrelation to at least one electrode contact. An arrangement for aplurality of bus lines from the electrode contact may be determined,e.g. so that the plurality of bus lines run substantially perpendicularto the determined equipotential lines. It should be noted that mappingequipotential lines does not necessarily require one pair of electrodes,and that equipotential lines may be determined for a single electrodeconfiguration as well.

An example of a 15 cm×15 cm OLED light panel, where the active area isdivided into 4 electrically separated sections with each one surroundedby heavy duty (wide) bus lines is shown in FIG. 6. Within each section,there are also fine gold bus lines, shown in FIG. 7. This is the panellayout reported in UDC publication “Levermore et al. Inf. Disp., Vol.26, No. 10, 2010”. For this OLED light panel, with total activearea=125.44 cm² and panel area=176.9 cm², FF≈71%. For this paneloperating at a luminance of 3,000 cd/m² (approximately 6,700 lm/m²), aU≈75% was found, prior to any aging. For the same panel U=92% at 1,000cd/m² (approximately 2,230 lm/m²) after aging to LT70 (70% of theinitial luminance). Considerable non-uniformity is observed at highluminance (even with relatively low FF) because of the non-optimizedcontact layout, where anode contacts are located on adjacent sidesrather than opposing sides of the emissive sections. Secondly, FF is lowdue to the relatively large area occupied by the bus lines.

The inventors have developed mathematical models which may be used todescribe design rules for bus line patterns to achieve optimized panelperformance. The bus lines on a large area light panel may be disposed,for example, into a uniform pattern, such as a grid pattern, or a stripepattern. The OLED light panel may then be divided into identical units,each unit composed of bus line part and OLED part.

Initially, we consider a grid-pattern bus line layout for a large-arealight panel. A four-unit diagram of a grid-pattern bus line isillustrated in FIG. 8, where each individual OLED device is surroundedby metal bus lines. The following parameters are defined: length of theactive area (S), height of the active area (H) and the half width of themetal bus lines along both x and y direction (W_(x) and W_(y)). Ingeneral, these parameters can vary from unit to unit. Also defined arethe total length and width of the rectangular panel area; X (along xdirection) and Y (along y direction). Assuming the anode contact startsat y=0, and that the end unit of each column has perfect contact withthe electrode, then each column will be identical and the differencewill be just between the rows. The n^(th) unit is the one connected tothe anode contact, the 1^(st) unit is the farthest from the anodecontact, and the m^(th) unit is any arbitrary unit between the 1^(st)and n^(th) unit. Particularly, in a single-contact configuration, the1^(st) unit will be the unit connected to the cathode contact; in adouble-contact configuration, where the anodes are on opposite edges ofthe panel area, it will be at or around the center of the column. Forthe m^(th) unit in a column starting from the anode contact, the aboveparameters can be written as H_(m), S_(m), W_(x,m), W_(y,m). By varyingthe geometry values, both the resistances of bus lines and OLEDs can betuned and thus current differences within the panel can be manipulated.

Since the metal bus lines are much more conductive than the TCO anode,it may be assumed that current will be majorly delivered to the OLEDsthrough the surrounding bus lines. Thus, an equivalent circuitry can bebuilt for each row of units, as drawn in FIG. 9A, where R_(b,m) is themetal bus line resistance of the m^(th) unit, and I_(m) is the currentflowing through the m^(th) OLED device. It may also be assumed thecathode is highly conductive, i.e. R_(k)=0, as shown in FIG. 9B. Theequipotential lines are running substantially parallel to the contactsin this configuration. Note that each OLED may follow a basic circuitryas shown in FIG. 9B.

During panel level design, luminance uniformity (U) may be determined.The luminance (L) of each unit may be calculated from the currentdensity (J) in each unit using L vs. J data for an equivalent small areapixel. Generally, the small area pixel need only be functionally orstructurally equivalent to the panel, and does not need to be identical.In practice, L is approximately linearly dependent on J. The greatestdifference in current density is expected between the unit closest tothe anode contact (J_(n)) and the unit farthest from the anode contact(J₁). Therefore, U can be obtained from the ratio between J₁ and J_(n),and hence L₁ and L. We then have U=L₁/L_(n)=L_(min)/=L_(max). Usingsimilar means the inventors have calculated the power efficacy (PE) ofthe OLED light panel. The power loss PL is determined by the ratio of IRloss in the bus line over the total power of the panel, which can beacquired by calculation of current density in each unit. Fill factor(FF) can also be easily calculated from the parameters in FIG. 8.Therefore, by inputting those geometry variables, they were still ableto have the output of panel uniformity, power efficacy (and hence powerloss) and fill factor, and could choose the best combination of theresults. The following explains further details of an exemplary bus linemodel.

According to the equivalent circuit drawn in FIG. 9B, we have:ΔV _(m) =V _(m+1) −V _(m) =R _(b,m) ·I _(m)  Eq. 1

Eq. 1 describes the universal voltage drop between two adjacent unitsregardless of bus line layout. Where R_(b,m) is the bus line resistanceof m^(th) segment, and I_(m) is the current flowing through thissegment. In general, if the bus line is running along y direction, andeach segment has a resistivity ρ(y), thickness t(y), and width W_(x)(y),and an angle θ(y) with respect to y, the total voltage drop for a busline of length L can be further described as:

${\Delta\; V} = {\int_{0}^{L}{{\rho(y)}\frac{{\overset{\rightarrow}{I}(y)}}{\cos^{2}{\theta(y)}{{{\overset{\rightarrow}{W}}_{x}(y)}}{t(y)}}{{\mathbb{d}y}}}}$For a particular grid-pattern bus line layout, where each pixel is in arectangular shape, Eq. 1 can be further written as:

I_(m) = J_(m) ⋅ A_(m) = J_(m) ⋅ H_(m) ⋅ S_(m)$V_{m + 1} = {{V_{m} + {R_{b,m} \cdot {\sum\limits_{i = 1}^{m}I_{i}}}} = {V_{m} + {R_{b,m} \cdot {\sum\limits_{i = 1}^{m}{J_{i} \cdot H_{i} \cdot S_{i}}}}}}$

For each OLED device, an exponential equation can be used to model thecurrent as a function of voltage as below:J=e ^(1+bV+cV) ²   Eq. 2J is the current density flowing through the device, V is the drivingvoltage between anode and cathode, a, b and c are constants dependent ondevice structure and working conditions, and they can be extracted froma JVL curve of an equivalent small area pixel.

Similarly, the relationship between J and L from the JVL curve can beextracted as:L=C _(o) +C ₁ ·J+C ₂ ·J ²  Eq. 3where C_(o), C₁ and C₂ are constants, decided by the device structure.This relation may be used to calculate power efficacy. Note that,depending on the JVL curve and accuracy requirements, the J-V and J-Lfunctions can be varied.

To calculate the bus line resistance, the inventors have further dividedthe metal bus line frames into segments A and B (shown in FIG. 10), andthe equivalent resistance is 2A+B/2, such that:

$R_{b,m} = {R_{s\; b} \cdot \left( {\frac{2W_{y,m}}{S_{m} + {2W_{x,m}}} + \frac{H_{m}}{2W_{y,m}}} \right)}$

R_(sb) is the sheet resistance of metal bus lines. This is determined bythe resistivity ρ_(b) and thickness t_(b) of the metal as follows:

$R_{s\; b} = \frac{\rho_{b}}{t_{b}}$

If given initial values V₁, J₁, W_(x1), W_(y1), S₁ and H₁, V₂ can becalculated as:

I₁ = J₁ ⋅ H₁ ⋅ S₁$V_{2} = {{V_{1} + {R_{b,1}I_{1}}} = {V_{1} + {I_{1}{R_{s\; b} \cdot \left( {\frac{2W_{y,t}}{S_{1} + {2W_{x,1}}} + \frac{H_{1}}{2W_{y,1}}} \right)}}}}$

Then, using Eq. 2, J₂ can be acquired and hence L₂ calculated from Eq.3. Next, V₃ can be calculated from V₂, J₂, W_(x2), W_(y2), H₂ and S₂.Therefore, by iterative calculation, current density and luminance ofeach unit can be acquired and uniformity U=L₁/L_(n)=L_(min)/L_(max) aswell.

Note that, in the typical operation range of interest, L can beconsidered linearly dependent on J. This is because in a well-designedpanel with high uniformity there is very little variation in J or L, soluminous efficiency (cd/A) is approximately constant. Therefore,U=L_(min)/L_(max)≈J_(min)/J_(max). This simplifies the uniformitycalculation procedure.

The model above describes a general case for grid-pattern, which meansH, S, W_(x) and W_(y) can vary according to different m. One simplifiedsituation is to have these variables independent of m:H _(m) =H,S _(m) =S,W _(x,m) =W _(x) ,W _(y,m) =W _(y)that is to say, each unit will be identical across the entire panel. Inthis case, Eq. 1 can be rewritten as:

$V_{m + 1} = {{V_{m} + {R_{b,m}I_{m}}} = {V_{m} + {{HSR}_{s\; b} \cdot \left( {\frac{2W_{y}}{S + {2W_{x}}} + \frac{H}{2W_{y}}} \right) \cdot {\sum\limits_{i = 1}^{m}J_{i}}}}}$

In certain circumstances, a uniform grid pattern may be more acceptablein terms of visual appearance. One advantage of forming grid-pattern busline is that fuses can be added to each pixel to prevent shortingwithout reducing Fill Factor. This is because, when integrating fuses,each pixel needs to be isolated from each other, which leavesnon-emissive gaps on all four sides in between the adjacent pixels Thesegaps can be filled with bus lines to improve the current distributionwhile Fill Factor is not affected.

The power efficacy (PE) can be calculated as follows:

${P\; E} = {\eta = {\frac{\pi}{V_{n}}\frac{\sum\limits_{m = 1}^{n}L_{m}}{\sum\limits_{m = 1}^{n}I_{m}}}}$where V_(n) is the voltage of the last OLED, i.e. the total inputvoltage,

$\sum\limits_{m = 1}^{n}I_{m}$and is the total input current.

The IR power loss (PL) caused by bus line resistance can be calculatedas:

${P\; L} = \frac{\sum\limits_{m = 1}^{n}{\left( {\sum\limits_{i = 1}^{m}I_{i}} \right)^{2} \cdot R_{b,m}}}{V_{n} \cdot {\sum\limits_{m = 1}^{n}I_{m}}}$

This is expressed as a percentage of the power dissipated in the buslines relative to the total input power.

As noted previously, FF may be understood as FF=(Panel Area−Bus LineArea)/Panel Area, where Panel Area is the area defined by the outline ofthe total plurality of Active Areas with surrounding Bus Line Areas. BusLine Area includes surface area of bus lines and insulating coverage(optional). In general, Fill Factor of a rectangular panel area withpanel length X and width Y can be defined as follows:

${F\; F} = \frac{{X \cdot Y} - {\sum\limits_{m = 1}^{n}A_{m}}}{X \cdot Y}$where A_(m) is the non-active surface area within the panel area causedby the presence of each bus line segment (this may include the bus lineand the insulating material that covers the bus line).

In order to prevent shorting, an insulating layer is normally disposedto cover the electrodes. The inventors define PI as the width ofinsulating material that covers the edge of each side of bus line. Sincethis extended region is not emissive, it reduces the active area. Takingthis into consideration, FF in this particular case can be written as:

${F\; F} = \frac{\left( {S - {PI}} \right)\left( {H - {PI}} \right)}{\left( {S + {2W_{x}}} \right)\left( {H + {2W_{y}}} \right)}$

An exemplary model has now been described, and parameters have beendefined. The next step is to use the model to develop bus line designrules.

It is clear that the wider the bus lines are, i.e. the greater W_(x) andW_(y), the lower FF. On the other hand, FF is also strongly dependent onpixel size. Taking a square pattern as an example, where H=S,W_(x)=W_(y), FIG. 11 plots FF as a function of W_(x) (W_(y)), for H=S=1mm (squares) and H=S=10 mm (circles). It is found that FF is lesssensitive to the change of W_(x) (W_(y)) when pixel size is relativelysmall. This implies that large size pixel may be desired in this casewhere wider bus lines can be disposed to improve U without losing toomuch FF.

FIGS. 12A and 12B further compare non-uniformity (NU=1−U) and power loss(PL) as a function of W_(x) with a fixed W_(y) or vice versa, for activearea unit size=1 mm×1 mm (FIG. 12A) and 10 mm×10 mm (FIG. 12B). Assumingthe anode contact runs along the x-axis at y=0, it is found that thevariation of W_(y) (width of bus lines running along x parallel to theanode contact) have little impact on NU or PL, however, NU and PLdecrease dramatically as W_(x) (width of bus lines running along yperpendicular to anode contact) increases up to 200 microns. Thisclearly shows that bus lines running perpendicular to the anode contactinto the active area play the critical role in determining NU and PL.Note that equipotential lines are running parallel to the contacts, andthis implies bus lines running perpendicular to equipotential lines ismore effective in enhancing uniformity.

Bus lines running parallel to the equipotential lines have been found todo relatively little to reduce NU and PL. Therefore, in embodiments, buslines should be placed perpendicular to equipotential lines to mosteffectively distribute currents. In this case, bus lines should berunning perpendicular to the contacts. The equipotential lines aredetermined by the position of electrode contacts. For instance, in asquare panel area where anode contacts are almost all around the fouredges, equipotential lines are a group of rings, as shown in FIG. 13. Inthis case, bus lines may be designed as a grid pattern to runperpendicularly across the equipotential lines, as shown in FIG. 14.

Another example is shown in FIG. 15, where the panel area iscircle-shape with anode contacts all around the circumference. Theequipotential lines in this circumstance are concentric circles, and buslines therefore should be designed along the radius from edge to thecenter. In addition, it should be noted that the size of active areaunit also affects FF and PL, where the bigger the unit size, the more NUand PL arise.

Since the horizontal bus lines have been found to have little impact interms of distributing current when the equipotential lines arehorizontal as explained above, a stripe design, where W_(y)=0, may beused to help enhance the fill factor. For example, the inventors havechosen a phosphorescent small area device, which has the JV curve fittedaccording to the expression below:J=e ^(−19.02+7.44·V−0.63·) ²

This small area pixel operates at 3,000 cd/m² (inclusive of 1.5× lightextraction enhancement) with V=4.33 V, and J=4.18 mA/cm². The bus linemetal has a resistivity of 2.44×10⁻⁶ Ohm-m and thickness of 600 nm(equivalent sheet resistance of 0.004 Ohm/sq).

Using a target uniformity criteria of U>80%, the inventors have beenable to find a FF=92.7%, when each stripe has anode width S=14 mm, halfbus line width W_(x)=0.55 mm, an insulating material (as an example)extends PI=0.03 mm beyond the bus line edge, as illustrated in FIG. 16.The total length of anode, bus line and insulating material of eachstripe is 134 mm, with anode contacts on top and bottom sides. Higher FFcan be achieved by reducing PI width. Simulated uniformity (from one endof the stripe to the center) is about 84% and PL along the bus line isabout 0.668%. As mentioned previously, total panel non-uniformity is theproduct of non-uniformity that arises from potential drops along buslines and non-uniformity that arises from potential drops across activeareas. The non-uniformity within each stripe was therefore investigatedusing a simulation process of one-dimensional bus line-free pixelperformance. Resistivity ρ_(a) and thickness t_(a) of anode material(e.g. ITO) are required in this simulation. Uniformity of 96% with0.367% power loss calculated within each stripe, where anode width S=14mm, resistivity ρ_(a)=1.8×10⁻⁶ Ohm-m and thickness t_(a)=120 nm(equivalent sheet resistance of 15 Ohm/sq). Hence, the total expecteduniformity is U=84%×96%≈81%, and the worst scenario for power loss inthe bus lines and pixel area combined is PL=1−(1−0668%)×(1−0.367%)≈1%.

The inventors also note that, in practice, the central region of a largearea light panel usually has slightly higher temperature than the outeredges. This higher temperature reduces the resistance of the OLED stack,which in turn compensates somewhat for the potential drop in the centerof the panel. This leads to greater luminance in the center of the panelthan predicted by the model, which in turn leads to improved U.

Based on a stripe design, the inventors fabricated a 15 cm×15 cm OLEDlighting panel with 9 lighting stripes connected in parallel throughgold bus lines using the same simulated device structure. There wereanode contacts at the left and right sides of each stripe, and cathodecontacts on the other two sides of the panel area. This double-contactconfiguration may be useful, for example, in improving luminanceuniformity relative to an equivalent panel with just one contact of eachpolarity. The anode contacts were also designed to contact both ends ofall 9 stripes such that there is negligible potential drop in deliveringthe charge to the start of each bus line. This electrode contact designhelps to ensure that the minimum bus line width may be used, therebyenabling high FF. The active area of each stripe was 14.15 mm wide and133.78 mm long, and the bus line was 1.1 mm wide. The FF of this panelwas about 92.8%. Note that in order to maximize uniformity within theactive area, it is preferred that where the active areas are rectangularwith sides of different lengths, the bus lines run parallel to the sideof greater length. Also note that where the panel area is rectangularwith sides of different lengths, it is preferred that the bus lines runperpendicular to the side of greater length.

Each OLED stripe has a device stack formed by vacuum thermal evaporation(VTE) deposition onto a soda lime glass substrate having an appropriaterefractive index, e.g. n=1.5, as illustrated in FIG. 17. Each OLEDincludes, in order, an anode (1200 Å thick ITO), a hole injection layer(100 Å thick LG101, available from LG Chemicals of Korea), a holetransport layer (3800 Å thick NPD), a first emissive layer (200 Å thickHost B doped with 24% Green Dopant A and 0.6% Red Dopant A), a secondemissive layer (75 Å thick Blue Host A doped with 20% Blue Dopant A), ablocking layer (50 Å thick Blue Host A), a layer (450 Å thick layer ofLG201, available from LG Chemicals of Korea and 40% LiQ), and a cathode(10 Å thick layer of LiQ (lithium quinolate) and a 1000 Å thick layer ofAl). Some examples of OLED materials that may be used to form the devicestack are also discussed further below.

The light emitting panel has a color rendering index (CRI) R_(a)>80, anda Duv<0.010. In CIE 1931 (x, y) color space, the MacAdam ellipse sizevaries with color temperature, dependent on the photopic response of thehuman eye. In order to compare differences in color, it is thereforeinstructive to convert into CIE 1976 (u′, v′) color space, wherecoordinate differences are approximately proportional to perceived colordifferences. The conversion is very simple: u′=4x/(−2x+12y+3) andv′=9y/(−2x+12y+3). A measure known as Duv=(Δu′²+ΔV′²)^(1/2) can then beused to quantify how far the chromaticity of a light source lies fromthe blackbody curve. As a general rule, when designing an OLED lightingpanel, one should target a Duv<0.010, or more preferably Duv<0.006.

Luminance was measured at normal incidence at 5 mA/cm² current densityat 9 points on the panel, as shown in FIG. 18. The particular drivingconditions were chosen such that average luminous emittance from thepanel as measured inside a 20″ integrating sphere was approximately8,700 μm/m² (inclusive of 1.5× light extraction enhancement). Table 2lists luminance at each of the 9 points.

TABLE 2 Luminance of 9 points at J = 5 mA/cm² of the panel in FIG. 15. 12 3 4 5 6 7 8 9 Lumi- 2720 2900 3010 2710 2850 2880 2730 2920 3050 nance(cd/m²)

Uniformity measured across the entire light panel U=L_(min)/L_(max) is89%. Note that in reality, the central region of the panel area normallyhas higher temperature than the edges due to the poorer heatdissipation, and this results in a larger current through the OLED.Therefore, the central region of the panel area is brighter thansimulated result and this leads to a slightly higher uniformity numberthan predicted by the model. Within each stripe, luminance uniformityachieves 97% in average.

Table 3 summarizes the luminance and fill factor from references,simulation and measurement from an optimized panel. Based on the model,the inventors have optimized bus line design for a 15 cm×15 cm OLEDlight panel, and improved the uniformity by about 20% with an enhancedfill factor by 31%, compared to REF 2.

TABLE 3 Summary of references, simulation and measurement. REF 1 REF 2SIM 1 DATA 1 Size 4″ 15 cm × 15 cm 15 cm × 15 cm 15 cm × 15 cm waferUniformity 78% 75%   81%   89% Fill Factor 98% 71% 92.7% 92.8%In view of the foregoing, several design objectives may be achieved, forexample, an OLED light panel may be manufactured with a panel area>50cm² and (1) FF>70% and U>80%; (2) FF>80 and U>90%; or (3) FF>90% andU>90%.(B) Optimization of Large Area OLED Light Panel FF, U and PE Using BusLines of Variable Width.

In principle, luminance non-uniformity is caused by the voltagedifference at each OLED sub-pixel. If we look into the general bus lineEq. 1 again

${\Delta\; V_{m}} = {\left. {R_{b,m} \cdot I_{m}}\Rightarrow V_{m + 1} \right. = {V_{m} + {R_{b,m} \cdot {\sum\limits_{i = 1}^{m}I_{i}}}}}$

It can be seen that the voltage drop ΔV_(m) between neighboring unitsbecomes greater as m increases (the greater the m is, the closer it isto the anode contact). This means that the voltage variation betweenadjacent units is more significant closer to the electrode contact, i.e.the current source. This is because when travelling away from thecontact, the current will be dissipated along the bus lines, and hencebecome smaller and smaller as it flows farther. If the bus line isuniform (i.e. R_(b,m) is a constant), then the voltage drop on the busline I×R is linearly dependent on the current. Since the current isgreatest near the contact region, the IR loss, i.e. the voltage drop,will be the greatest accordingly. As is known that luminance isdetermined by the voltage and the current, the large variation ofvoltage along bus lines causes the luminance non-uniformity. Forinstance, assuming a grid-pattern where each unit is identical, usingthe same device data and working condition as described in the previoussection, normalized luminance can be plotted as a function of distancefrom the anode contact, X, in FIG. 19. Also plotted in FIG. 19 is thefirst derivative of the normalized luminance, reflecting the luminancegradient dL/dX. It can be seen that for a uniform-patterned bus linelayout, the luminance gradient is greater near the contact than fartheraway. This means the luminance change along the bus lines is moredramatic near the contact regions due to the greater voltage drop. TakeREF 1 panel as an example, the data in Table 1 shows that the luminancechanges between spots 1 and 3 ΔL₁₃ is 8.0%, while that between spots 3and 6 ΔL₃₆ is 3.6%, which gives ΔL₃₆/ΔL₁₃=0.45.

In order to reduce the dramatic luminance variation at the contact,lower IR loss is required near the electrode contacts. This can beachieved by enhancing the conductance of the bus lines, i.e. lower R,near electrodes contact regions. The conductance of bus lines can betuned by, for example, using a more conductive metal, increasing thethickness, or the width. In practice, with a fixed bus line thicknessand material type, a non-uniform layout is desired where the bus linesare wider at the anode contact end to ensure a lower resistance.

Generally, the luminance gradient along bus lines can be controlled bydesigning a non-uniform bus line pattern. In particular, a constantluminance gradient dL/dX=constant, or the ratio between minimum andmaximum gradient (dL/dX)_(min)/(dL/dX)_(max)>0.5, may be desired wherethe luminance change is not too dramatic for two neighboring units alongthe bus lines. Since the current becomes lower for OLED units fartheraway from the contact, bus line resistance therefore is allowed to begreater for the same IR drop. The bus lines can then be made narrowerclose to the farther end of the contact.

Another advantage of introducing non-uniform patterned bus lines is thatwith the same surface area of bus line metal at a fixed thickness, i.e.same FF, the luminance uniformity across the same length of OLED deviceis better than using a uniform bus line pattern. As a comparison withthe uniform-stripe pattern, the bus lines can be designed to have atapered shape with a double-contact configuration, as illustrated inFIG. 20. The model is accordingly modified to simulate this non-uniformcase. Instead of having a constant bus line width W_(x), an increment Δis added to the bus line width of each unit:W _(x,m+1) =W _(x,m)+Δ

At the same time, the active area will shrink by Δ·H, due to theincrease of bus line width. If given an initial W_(x,o), the surfacearea of metal can be calculated. The combination of W_(x,o) and Δ needsto be tuned to keep the surface area the same as that in theuniform-stripe design.

Using the same device data and working condition as described in theprevious section, the inventors calculated U and PL at variouscombination of W_(x,o) and Δ, as a comparison to the uniform pattern, aslisted in Table 4. As an example, bus lines A, B, and C are drawn inFIG. 21. It can be seen that bus lines with tapered shape have betterluminance uniformity and less power loss than the uniform stripe shape.In particular, a preferred mode exists for the tapered bus line. In thisexample, the combination of W_(x,o)=0.02 mm and Δ=0.0161 mm, has beenfound to enable the highest U=89.1%, and the least PL=0.495%. Thenormalized luminance and luminance gradient at this combination isplotted in FIG. 22. Compared to FIG. 19, the luminance has a more evenvariation along the bus line, and the gradient is almost constant. Thetapered bus line therefore enables greater U compared to a uniform busline layout.

TABLE 4 Comparison of U and PL at various combination of W_(x, o) and Δ,with the uniform pattern. Example Δ [mm] U PL Uniform W_(x) [mm] A 0.5500.0000 84.0% 0.668% Tapered W_(xo) B 0.002 0.0166 89.0% 0.497% 0.0200.0161 89.1% 0.495% 0.220 0.0100 88.4% 0.527% C 0.400 0.0046 86.4%0.588%

Alternatively, if keeping the same luminance uniformity performance,less metal is required in a non-uniform bus line pattern than a uniformone. By varying the bus line widths, not only the voltage drop can bebalanced, but the Fill Factor can be enhanced as well.

An example of non-uniform-patterned bus line is shown in FIG. 23. Inthis example, a multi-contact configuration is applied where anodecontacts are on all four sides of the panel. Metal bus lines areconducting current from surrounding contacts toward the center of theplate with a reduced widths forming a spiral shape. A device stack asillustrated in FIG. 17 was used to fabricate the OLED lighting panel ona 15 cm×15 cm soda lime glass substrate. The metal bus line is 4000 Åthick aluminum, the sheet resistance of which is about 0.05 ohm/square.The luminance of different points (numbered in FIG. 23) measured at 5mA/cm² current density are listed in Table 5.

TABLE 5 Luminance of 9 spots at 5 mA/cm² current density of the panel inFIG. 19. 1 2 3 4 5 6 7 8 9 Lumi- 1360 1410 1390 1410 1420 1390 1400 13801400 nance (cd/m²)

As can be extracted from the luminance data, the uniformity along thebus line of this spiral shaped panel is 96.5% in average. Moreimportantly, the luminance variation along the bus lines follows aconstant gradient, about 0.04%/mm in average.

In conclusion, to get the highest uniformity, the inventors haveproposed and developed various methods to minimize the overall potentialdrop along the bus line of a length L, which takes consideration of allthe parameters involved: panel area dimension, required luminousemittance, dimensions of the bus lines, resistivity and thickness of thebus line material and the electrode, variation and orientation of thebus line, JVL characteristic of an equivalent small area pixel etc, asshown in the following equation:

${\Delta\; V} = {\int_{0}^{L}{{\rho(y)}\frac{{\overset{\rightarrow}{I}(y)}}{\cos^{2}{\theta(y)}{{{\overset{\rightarrow}{W}}_{x}(y)}}{t(y)}}{{\mathbb{d}y}}}}$where at position y, ρ(y) is the resistivity of the bus line metal, I(y)is the current, W_(x)(y) is the width of the bus line, t(y) is thethickness of the bus line and θ(y) is the angle between current flowingdirection and y direction.

It should be noted that, in various embodiments such as those depictedin FIGS. 13, 14, 15, 18, 20 and 23, the electrode contacts may extend toor beyond the border of the active area(s). That is, a “footprint” setby the outermost dimensions of the electrode contacts may be equal to orgreater than a footprint of the panel area outer border.

An organic light emitting device is also provided including features asdescribed herein. The device may include an anode, a cathode, and anorganic emissive layer disposed between the anode and the cathode. Theorganic emissive layer may include a host and a phosphorescent dopant,exemplary materials of which are discussed further below.

According to aspects of the present subject matter, the inventors havesuccessfully fabricated, for example, a 15 cm×15 cm OLED light panel onan ITO anode with sheet resistance≈15 Ohm/sq. There were 9 individualactive areas, each one a stripe measuring 13.378 cm×1.415 cm=18.930 cm²,which gives total active area=170.369 cm². The individual active area inthe example is almost 20 times greater than taught by other devices. Thepanel area for the layout in this work is 183.587 cm², which givesFF≈92.8% and Uniformity>95% within each individual active area, and U isalso substantially higher than in previous work.

Combination with Other Materials

The materials described herein as useful for a particular layer in anorganic light emitting device may be used in combination with a widevariety of other materials present in the device. For example, emissivedopants disclosed herein may be used in conjunction with a wide varietyof hosts, transport layers, blocking layers, injection layers,electrodes and other layers that may be present. The materials describedor referred to below are non-limiting examples of materials that may beuseful in combination with the compounds disclosed herein, and one ofskill in the art can readily consult the literature to identify othermaterials that may be useful in combination.

HIL/HTL:

A hole injecting/transporting material to be used in the presentinvention is not particularly limited, and any compound may be used aslong as the compound is typically used as a hole injecting/transportingmaterial. Examples of the material include, but not limit to: aphthalocyanine or porphryin derivative; an aromatic amine derivative; anindolocarbazole derivative; a polymer containing fluorohydrocarbon; apolymer with conductivity dopants; a conducting polymer, such asPEDOT/PSS; a self-assembly monomer derived from compounds such asphosphonic acid and sliane derivatives; a metal oxide derivative, suchas MoO_(x); a p-type semiconducting organic compound, such as1,4,5,8,9,12-Hexaazatriphenylenehexacarbonitrile; a metal complex, and across-linkable compounds.

Examples of aromatic amine derivatives used in HIL or HTL include, butnot limit to the following general structures:

Each of Ar¹ to Ar⁹ is selected from the group consisting aromatichydrocarbon cyclic compounds such as benzene, biphenyl, triphenyl,triphenylene, naphthalene, anthracene, phenalene, phenanthrene,fluorene, pyrene, chrysene, perylene, azulene; group consisting aromaticheterocyclic compounds such as dibenzothiophene, dibenzofuran,dibenzoselenophene, furan, thiophene, benzofuran, benzothiophene,benzoselenophene, carbazole, indolocarbazole, pyridylindole,pyrrolodipyridine, pyrazole, imidazole, triazole, oxazole, thiazole,oxadiazole, oxatriazole, dioxazole, thiadiazole, pyridine, pyridazine,pyrimidine, pyrazine, triazine, oxazine, oxathiazine, oxadiazine,indole, benzimidazole, indazole, indoxazine, benzoxazole, benzisoxazole,benzothiazole, quinoline, isoquinoline, cinnoline, quinazoline,quinoxaline, naphthyridine, phthalazine, pteridine, xanthene, acridine,phenazine, phenothiazine, phenoxazine, benzofuropyridine,furodipyridine, benzothienopyridine, thienodipyridine,benzoselenophenopyridine, and selenophenodipyridine; and groupconsisting 2 to 10 cyclic structural units which are groups of the sametype or different types selected from the aromatic hydrocarbon cyclicgroup and the aromatic heterocyclic group and are bonded to each otherdirectly or via at least one of oxygen atom, nitrogen atom, sulfur atom,silicon atom, phosphorus atom, boron atom, chain structural unit and thealiphatic cyclic group. Wherein each Ar is further substituted by asubstituent selected from the group consisting of hydrogen, deuterium,halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy,amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl,heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile,isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinationsthereof.

In one aspect, Ar¹ to Ar⁹ is independently selected from the groupconsisting of:

k is an integer from 1 to 20; X¹ to X⁸ is CH or N; Ar¹ has the samegroup defined above.

Examples of metal complexes used in HIL or HTL include, but not limit tothe following general formula:

M is a metal, having an atomic weight greater than 40; (Y¹—Y²) is abindentate ligand, Y1 and Y² are independently selected from C, N, O, P,and S; L is an ancillary ligand; m is an integer value from 1 to themaximum number of ligands that may be attached to the metal; and m+n isthe maximum number of ligands that may be attached to the metal.

In one aspect, (Y¹—Y²) is a 2-phenylpyridine derivative.

In another aspect, (Y¹—Y²) is a carbene ligand.

In another aspect, M is selected from Ir, Pt, Os, and Zn.

In a further aspect, the metal complex has a smallest oxidationpotential in solution vs. Fc⁺/Fc couple less than about 0.6 V.

Host:

The light emitting layer of the organic EL device of the presentinvention preferably contains at least a metal complex as light emittingmaterial, and may contain a host material using the metal complex as adopant material. Examples of the host material are not particularlylimited, and any metal complexes or organic compounds may be used aslong as the triplet energy of the host is larger than that of thedopant.

Examples of metal complexes used as host are preferred to have thefollowing general formula:

M is a metal; (Y³—Y⁴) is a bindentate ligand, Y³ and Y⁴ areindependently selected from C, N, O, P, and S; L is an ancillary ligand;m is an integer value from 1 to the maximum number of ligands that maybe attached to the metal; and m+n is the maximum number of ligands thatmay be attached to the metal.

In one aspect, the metal complexes are:

(O—N) is a bidentate ligand, having metal coordinated to atoms O and N.

In another aspect, M is selected from Ir and Pt.

In a further aspect, (Y³—Y⁴) is a carbene ligand.

Examples of organic compounds used as host are selected from the groupconsisting aromatic hydrocarbon cyclic compounds such as benzene,biphenyl, triphenyl, triphenylene, naphthalene, anthracene, phenalene,phenanthrene, fluorene, pyrene, chrysene, perylene, azulene; groupconsisting aromatic heterocyclic compounds such as dibenzothiophene,dibenzofuran, dibenzoselenophene, furan, thiophene, benzofuran,benzothiophene, benzoselenophene, carbazole, indolocarbazole,pyridylindole, pyrrolodipyridine, pyrazole, imidazole, triazole,oxazole, thiazole, oxadiazole, oxatriazole, dioxazole, thiadiazole,pyridine, pyridazine, pyrimidine, pyrazine, triazine, oxazine,oxathiazine, oxadiazine, indole, benzimidazole, indazole, indoxazine,benzoxazole, benzisoxazole, benzothiazole, quinoline, isoquinoline,cinnoline, quinazoline, quinoxaline, naphthyridine, phthalazine,pteridine, xanthene, acridine, phenazine, phenothiazine, phenoxazine,benzofuropyridine, furodipyridine, benzothienopyridine,thienodipyridine, benzoselenophenopyridine, and selenophenodipyridine;and group consisting 2 to 10 cyclic structural units which are groups ofthe same type or different types selected from the aromatic hydrocarboncyclic group and the aromatic heterocyclic group and are bonded to eachother directly or via at least one of oxygen atom, nitrogen atom, sulfuratom, silicon atom, phosphorus atom, boron atom, chain structural unitand the aliphatic cyclic group. Wherein each group is furthersubstituted by a substituent selected from the group consisting ofhydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl,alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl,alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester,nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, andcombinations thereof.

In one aspect, host compound contains at least one of the followinggroups in the molecule:

R¹ to R⁷ is independently selected from the group consisting ofhydrogen, alkyl, alkoxy, amino, alkenyl, alkynyl, arylalkyl,heteroalkyl, aryl and heteroaryl, when it is aryl or heteroaryl, it hasthe similar definition as Ar's mentioned above.

k is an integer from 0 to 20.

X¹ to X⁸ is selected from CH or N.

HBL:

A hole blocking layer (HBL) may be used to reduce the number of holesand/or excitons that leave the emissive layer. The presence of such ablocking layer in a device may result in substantially higherefficiencies as compared to a similar device lacking a blocking layer.Also, a blocking layer may be used to confine emission to a desiredregion of an OLED.

In one aspect, compound used in HBL contains the same molecule used ashost described above.

In another aspect, compound used in HBL contains at least one of thefollowing groups in the molecule:

k is an integer from 0 to 20; L is an ancillary ligand, m is an integerfrom 1 to 3.

ETL:

Electron transport layer (ETL) may include a material capable oftransporting electrons. Electron transport layer may be intrinsic(undoped), or doped. Doping may be used to enhance conductivity.Examples of the ETL material are not particularly limited, and any metalcomplexes or organic compounds may be used as long as they are typicallyused to transport electrons.

In one aspect, compound used in ETL contains at least one of thefollowing groups in the molecule:

R¹ is selected from the group consisting of hydrogen, alkyl, alkoxy,amino, alkenyl, alkynyl, arylalkyl, heteroalkyl, aryl and heteroaryl,when it is aryl or heteroaryl, it has the similar definition as Ar'smentioned above.

Ar¹ to Ar³ has the similar definition as Ar's mentioned above.

k is an integer from 0 to 20.

X¹ to X⁸ is selected from CH or N.

In another aspect, the metal complexes used in ETL contains, but notlimit to the following general formula:

(O—N) or (N—N) is a bidentate ligand, having metal coordinated to atomsO, N or N, N; L is an ancillary ligand; m is an integer value from 1 tothe maximum number of ligands that may be attached to the metal.

In any above-mentioned compounds used in each layer of the OLED device,the hydrogen atoms can be partially or fully deuterated.

In addition to and/or in combination with the materials disclosedherein, many hole injection materials, hole transporting materials, hostmaterials, dopant materials, exiton/hole blocking layer materials,electron transporting and electron injecting materials may be used in anOLED. Non-limiting examples of the materials that may be used in an OLEDin combination with materials disclosed herein are listed in Table XXXbelow. Table XXX lists non-limiting classes of materials, non-limitingexamples of compounds for each class, and references that disclose thematerials.

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It is understood that the various embodiments described herein are byway of example only, and are not intended to limit the scope of theinvention. For example, many of the materials and structures describedherein may be substituted with other materials and structures withoutdeviating from the spirit of the invention. The present invention asclaimed may therefore includes variations from the particular examplesand preferred embodiments described herein, as will be apparent to oneof skill in the art. It is understood that various theories as to whythe invention works are not intended to be limiting.

The invention claimed is:
 1. A method of manufacturing a light emittingpanel with a plurality of active areas and a plurality of bus lines, themethod comprising: determining equipotential lines in the absence of buslines, on at least one electrode between at least one pair of electrodecontacts with the same electrical polarity; determining an arrangementfor a plurality of bus lines between the at least one pair of electrodecontacts, the plurality of bus lines arranged to run perpendicular tothe determined equipotential lines; and forming the plurality of buslines in electrical contact with the at least one electrode according tothe determined arrangement.
 2. The method of claim 1, wherein the atleast one pair of electrode contacts includes a pair of anode contacts,the at least one electrode is an anode, and the plurality of bus linesare arranged between the pair of anode contacts.
 3. The method of claim1, wherein the at least one pair of electrode contacts includes a pairof cathode contacts, the at least one electrode is a cathode, and theplurality of bus lines are arranged between the pair of cathodecontacts.
 4. The method of claim 1, wherein: a panel area isrectangular; the at least one pair of electrode contacts includescontacts of the same polarity on each side of the panel area; theplurality of bus lines are arranged such that a first set of the buslines closely run perpendicular to one pair of opposing sides of thepanel area, and a second set of the bus lines closely run perpendicularto the other pair of opposing sides of the panel area; and the first setof the bus lines and the second set of the bus lines are in electricalcontact with the at least one electrode.
 5. The method of claim 1,wherein: a panel area is rectangular; a first pair of opposing sides ofthe panel area have a relatively long length compared to a second pairof opposing sides of the panel area; the at least one pair of electrodecontacts includes contacts of the same polarity on at least the firstpair of opposing sides of the panel area; and the plurality of bus linesare arranged to closely run only perpendicular to the first pair ofopposing sides of the panel area.
 6. The method of claim 1, wherein: apanel area includes a plurality of rectangular active areas; first pairsof opposing sides of the active areas have a relatively long lengthcompared to second pairs of opposing sides of the active areas; and theactive areas are arranged such that the first pair of opposing sides ofthe active areas closely run parallel to the plurality of bus lines. 7.The method of claim 1, wherein: a panel area comprises a circular shape;the equipotential lines are concentric; and the bus lines are arrangedto run along radii extending from an edge of the circular shape to acenter of the circular shape.
 8. The method of claim 1, wherein afootprint of the outer dimensions of the at least one pair of electrodecontacts is equal to or larger than a perimeter footprint of a panelarea.
 9. The method of claim 1, wherein: the at least one electrodeincludes a first electrode and a second electrode; equipotential linesare determined for the first electrode and the second electrode; the atleast one pair of electrode contacts includes a first set of electrodecontacts for the first electrode and a second set of electrode contactsfor the second electrode; wherein the first electrode is between thefirst set of electrode contacts and the second electrode is between thesecond set of electrode contacts; a first set of the plurality of buslines are arranged between the first set of electrode contacts and asecond set of the plurality of bus lines are arranged between the secondset of electrode contacts; and the first set of bus lines are formed inelectrical contact with the first electrode and the second set of buslines are formed in electrical contact with the second electrode. 10.The method of claim 9, wherein the first electrode is anode and thesecond electrode is cathode.
 11. The method of claim 1, wherein: a panelarea is rectangular; the at least one pair of electrode contactsincludes a first set of electrode contacts of the same electricalpolarity on opposite sides of the panel area; and the plurality of buslines are arranged in electrical contact with the at least one electrodeto closely run perpendicular to the first set of electrode contacts. 12.The method of claim 11, wherein: the at least one electrode includes afirst electrode and a second electrode, the second electrode separate,and opposite electrical polarity, from the first electrode; theequipotential lines are determined for the first electrode and thesecond electrode; the at least one pair of electrode contacts includesthe first set of electrode contacts, for the first electrode, and asecond set of electrode contacts, for the second electrode; a first setof the plurality of bus lines are arranged between the first set ofelectrode contacts; a second set of the plurality of bus lines arearranged between the second set of electrode contacts; the first set ofbus lines are formed in electrical contact with the first electrode andperpendicular to the first set of electrode contacts; and the second setof bus lines are formed in electrical contact with the second electrodeand perpendicular to the second set of electrode contacts.
 13. Themethod of claim 11, wherein the first set of electrode contacts areanode contacts.
 14. The method of claim 11, wherein the first set ofelectrode contacts are cathode contacts.
 15. The method of claim 1,further comprising calculating a minimum bus line width for theplurality bus lines based on a given working condition, wherein theplurality of bus lines are formed according to the calculated minimumbus line width.
 16. The method of claim 15, wherein the workingcondition includes a target luminous emittance, and one or thecombination of two of a minimum Uniformity, a minimum Fill Factor and amaximum Power Loss.
 17. The method of claim 16, wherein the calculatingthe minimum bus line width further comprises: providing device currentdensity-voltage-luminance (JVL) data of an equivalent small area pixel;providing horizontal dimensions of the panel area; providing resistivityvalues and thickness of bus line material and the electrode onto whichthe bus line is disposed; and optimizing values for at least one of amaximum Fill Factor (FF), a maximum luminance uniformity (U) and aminimum power loss (PL) for the target working condition.
 18. A methodof manufacturing a light emitting panel, wherein the panel areacomprises a plurality of active areas and a plurality of bus lines, themethod comprising: providing horizontal dimensions of the panel area;providing device current density-voltage-luminance (JVL) data of anequivalent small area pixel; providing resistivity values and thicknessof bus line material and an electrode onto which the bus line isdisposed; providing a target working condition for the light emittingpanel; calculating at least one width of metal bus lines based on thehorizontal dimensions of the panel area, device JVL data, resistivityand thickness of bus line material and the electrode onto which the busline is disposed, and the target working condition; and forming theplurality of bus lines according to the at least one calculated value.19. The method of claim 18, wherein the working condition includes atarget luminous emittance and one or the combination of two of a minimumuniformity, a minimum Fill Factor and a maximum power loss.
 20. Themethod of claim 18, wherein the calculating at least one width of metalbus lines comprises solving for a Fill Factor (FF)>70% and a LuminanceUniformity (U)>80%.
 21. The method of claim 18, wherein the lightemitting panel has a panel area >50 cm² and the calculating at least onewidth of metal bus lines comprises solving for a Fill Factor (FF)>80%and a Luminance Uniformity (U)>90%.
 22. The method of claim 18, whereinthe light emitting panel has a panel area >50 cm² and the calculating atleast one width of metal bus lines comprises solving for a Fill Factor(FF)>90% and a Luminance Uniformity (U)>90%.
 23. The method of claim 18,wherein the panel area is rectangular shaped with length X and width Y,the method further comprising solving for Fill Factor (FF) according tothe equation:${{F\; F} = \frac{{X \cdot Y} - {\sum\limits_{m = 1}^{n}A_{m}}}{X \cdot Y}},$wherein, A_(m) is the non-active surface area within the panel areacaused by the presence of each bus line segment.
 24. The method of claim18, wherein, with a bus line running along a y direction, each segmenthas a current I(y), resistivity p(y), thickness t(y), and widthW_(x)(y), and an angle θ(y) with respect to y, and the calculating theat least one width of metal bus lines comprises calculating the widthalong an x direction (W_(x)) and solving for a potential drop (ΔV) alongthe bus line of length L according to the equation:${\Delta\; V} = {\int_{0}^{L}{{\rho(y)}\frac{{\overset{\rightarrow}{I}(y)}}{\cos^{2}{\theta(y)}{{{\overset{\rightarrow}{W}}_{x}(y)}}{t(y)}}{{{\mathbb{d}y}}.}}}$25. The method of claim 18, wherein the bus lines are formed to runsubstantially perpendicular to the equipotential lines.
 26. The methodof claim 18, wherein: the panel area is rectangular and includes atleast one pair of electrode contacts of the same polarity on each sideof the panel area; the plurality of bus lines are arranged such that afirst set of the bus lines closely run perpendicular to one pair ofopposing sides of the panel area, and a second set of the bus linesclosely run perpendicular to the other pair of opposing sides of thepanel area; and the first set of the bus lines and the second set of thebus lines are in electrical contact with the at least one electrode. 27.The method of claim 18, wherein: the panel area is rectangular andincludes at least one pair of electrode contacts of the same polarity; afirst pair of opposing sides of the panel area have a relatively longlength compared to a second pair of opposing sides of the panel area;the at least one pair of electrode contacts includes contacts of thesame polarity on at least the first pair of opposing sides of the panelarea; and the plurality of bus lines are arranged to closely run onlyperpendicular to the first pair of opposing sides of the panel area. 28.The method of claim 18, wherein: the panel area includes a plurality ofrectangular active areas; first pairs of opposing sides of the activeareas have a relatively long length compared to second pairs of opposingsides of the active areas; and the active areas are arranged such thatthe first pair of opposing sides of the active areas closely runparallel to the plurality of bus lines.
 29. The method of claim 18,wherein the panel area operates at luminous emittance greater than 8,000lm/m² inclusive of light extraction enhancement.
 30. The method of claim18, wherein a footprint of outer dimensions of at least one pair ofelectrode contacts connected to the bus lines is equal to or larger thana perimeter footprint of the panel area.
 31. The method of claim 18,wherein the calculating at least one width of metal bus lines includesproviding a length of at least one active area (S) and a height of thisone active area (H).
 32. The method of claim 31, wherein the calculatingat least one width of metal bus lines includes calculating at least oneof a width of metal bus lines along an x direction (W_(x)) and width ofmetal bus lines along a y direction (W_(y)), based on S, H, horizontaldimensions of the panel area, device JVL data, resistivity and thicknessof bus line material and the electrode onto which the bus line isdisposed, and the target working condition.